What about a 64-bit architecture for the Cortex-M market? If they could pull off some wizardry in focusing on energy efficiency, and maybe target peripheral functions involving GPU-like parallel processors for small-scale ML/AI/etc. purposes?
I dunno, it seems like there might be a market for that sort of thing. You train your model, pop it on a chip that consumes microwatts per megahertz? Something like that could be appealing.
It might also be impossible. I don't design chips. But I do think targeting both mobility and parallel processing could be cool. Maybe something like what Parallella is doing.
64-Bit architectures and GPUs are totally different beasts requiring MMU's and OS's and whole development teams.
My last project used a 14 pin processor with 195 lines of bare metal C code compiling to 486 bytes of Flash memory and running on an internal 32Khz clock. This is more the target 8051 market though I must admit some cortex M0 processors are getting as cheap to use here.
The Propeller Chip is awesome (no interrupts and 8 processors is a really cool concept) but at $8 it is going against the big boys (Freescale/ST/Microchip) with their more flexible memory, power management and rich peripheral sets. I would love for one of the big players to licence the propeller core but it wont happen.
64 bit is expensive on memory bandwidth (and on size of memory as such,) and memory bandwidth costs a lot in terms of die size relative to microscopic size of MCU cores.
Most of MCU applications don't do much of computations as such
I dunno, it seems like there might be a market for that sort of thing. You train your model, pop it on a chip that consumes microwatts per megahertz? Something like that could be appealing.
It might also be impossible. I don't design chips. But I do think targeting both mobility and parallel processing could be cool. Maybe something like what Parallella is doing.